Electronic equipment furnished with a display device comprises, as shown in FIG. 9, a CPU (central processing unit) 51, a RAM (random access memory) 53 connected to a bus 52 extending from the CPU 51, an I/O (input/output interface) 54, and a display controller 55. A VRAM (Video RAM) 56 and a display device 60 are connected to the display controller 55, so that display data stored in the VRAM 56 are sent to the display device 60 to be displayed.
When the display device 60, for example, a 240-line direct matrix type liquid crystal display device, is driven line-sequentially by the average voltage driving method, one selected pulse and 239 non-selected pulses are applied to each liquid crystal element in one frame period, meaning that the non-selected pulses are applied to the liquid crystal element far longer than the selected pulse.
Thus, liquid crystal molecules forming the liquid crystal element respond not only to the selected pulse but also to the non-selected pulses, which is known as a frame response phenomenon. The frame response phenomenon is conspicuous when the liquid crystal element is made of a liquid crystal material with a relatively quick response, and the contrast degrades as a result. In case of a multi-level display using a level control circuit of a skipping method, the number of colors available for a color display increases; however, at the same time, there occur inconveniences such as contrast degradation and flickers on the screen.
As shown in FIG. 11, the higher the frame frequency, the better the contrast. This is because the frame cycle becomes shorter as the frame frequency rises, and the frame response phenomenon does not easily occur in a short frame cycle. In case of the multi-level display using the skipping method, a good image can be displayed on the screen with reduced flickers by raising the frame frequency as set forth in Table 1 below. In Table 1, the flickers are reduced more in the order of marks X.DELTA.o.
TABLE 1 ______________________________________ 60R ENCY (Hz) 120 180 240 300 ______________________________________ FLICKERS .DELTA. .smallcircle. .smallcircle. .smallcircle. ______________________________________
When a low-frequency driven display device and a high-frequency driven display device are connected to the above electronic equipment to display images simultaneously, the display quality of the latter degrades significantly due to the frame response phenomenon if the latter is timed to the former.
To eliminate this deficiency, a frame memory 57 is conventionally provided besides the VRAM 56 as shown in FIG. 12. To be more specific, the display controller 55 accesses the VRAM 56 by an original clock, while it accesses the frame memory 57 on a second clock generated by a clock divider 58, which is in sync with the original clock and has a frequency of an integral multiple of that of the original clock. Thus, a resulting display signal will have a second frame frequency which is an integral multiple of the original frame frequency. For example, when the original frame frequency is 60 Hz, then the second frame frequency is either 120 Hz, 180 Hz, 240 Hz, or 300 Hz, . . . .
Accordingly, the low-frequency driven display device displays an image at the original frame frequency, whereas the high-frequency driven display device displays an image at the second frame frequency which is an integral multiple of the original frame frequency. As a result, the frame response phenomenon occurring in the high-frequency driven display device can be eliminated.
However, according to the above structure, the second frame frequency is not a frame frequency such that enables the high-frequency driven display device to render the optimal display characteristics in most of the cases, thereby presenting a problem that ghosts or flickers appear on the screen.
Also, Japanese Laid-open Patent Application No. 6-67626/1994 discloses a structure as shown in FIG. 10: the frame frequency of an image signal S10 sent to a direct matrix type liquid crystal display device 62 from electronic equipment 61 on a host side is set to 80 Hz or more, so that the display quality is upgraded by reducing the frame response phenomenon. Thus, using this structure enables a high-contrast image display.
However, according to the above structure, the electronic equipment 61 on the host side must operate at a high-speed to output the image signal S10 of a high frame frequency to the liquid crystal display device 62. For this reason, the above structure demands high-speed memories and devices, which increases the manufacturing cost significantly. In addition, if the electronic equipment 61 on the host side is accelerated, it can not be driven at the same frame frequency driving a CRT (cathode ray tube) display device, the active matrix type liquid crystal display device or the like, thereby making it impossible to share the electronic equipment 61.
Further, there have been proposed some methods to drive the liquid crystal panel of a direct matrix type liquid crystal display device at a lower duty ratio, in which the screen of the liquid crystal panel (hereinafter referred to as the LCD) 41 is split into an upper half screen and a lower half screen to upgrade the display quality as shown in FIG. 14 accompanying with the present invention.
A first method is applied to a personal computer or the like, in which, as shown in FIG. 17, an LCD controller 68 interconnecting an LCD 65 and two VRAMs (video RAMS) each respectively serving as an upper half screen memory 66 and a lower half screen memory 67 is developed, so that the data for the upper half screen and lower half screen are outputted to the LCD 65 simultaneously from the upper half screen memory 66 and lower half screen memory 67, respectively.
A second method provides a driving device including a frame buffer memory for a liquid crystal display as is disclosed, for example, in Japanese Laid-open Patent Application No. 5-307370/1993.
More precisely, in the above driving device, an upper half screen block 71 and a lower half screen block 72, each storing their respective frame data and jointly forming a VRAM serving as a frame memory, are directly connected to an unillustrated driving driver of an LCD 70 as shown in FIG. 18. Also, a display controller 73 is connected to the upper half screen block 71 and lower half screen block 72. The display controller 73 outputs an address signal to access the upper half screen block 71 and lower half screen block 72, and a control signal to control the output of the display data to the LCD 70 from the upper half screen block 71 and lower half screen block 72.
This means that the electronic equipment on the host side outputs the display data without acknowledging whether the display data are to be stored in the upper half screen block 71 or lower half screen block 72 in the VRAM, but the display controller 73 must distinguish whether the display data are the data for the upper half screen or lower half screen to write the display data adequately into the upper half screen block 71 and lower half screen block 72 in the VRAM.
This is the reason why an address converting circuit 74 is provided to the conventional driving device. The address converting circuit 74 receives an address from the host to check whether the destination address of the display data from the host is in the upper half block 71 or lower half block 72, so that the display controller 73 accesses the upper half screen block 71 or lower half screen block 72 adequately to store the display data. If the address is in the upper half block 71, the address converting circuit 74 outputs the same intact; otherwise, it calculates a balance between the last address in the upper half screen block 71 and the leading address in the lower half screen block 72 in the VRAM, and adds the balance to the original address to output the adding result to the display controller 73.
According to this driving method, by providing the address converting circuit 74 before the conventional display controller 73, the host can access the VRAM in the same manner as the conventional method while the display data can be outputted sequentially to the upper half screen and lower half screen of the liquid crystal display device at the same timing.
However, according to the first method in which the LCD controller 68 is developed, it is necessary to design a complicated circuit and timing, thereby presenting a problem that it takes quite a long time and considerable efforts to develop the LCD controller 68.
More precisely, a dynamic RAM is used as a VRAM for a personal computer, whereas a dual port RAM is used as the VRAM for a workstation due to the need for a fast and accurate display. In case of the VRAM using the dynamic RAM, it is relatively easy to design the circuit and timing of the display controller, whereas in case of the VRAM using the dual port RAMs, or namely, the upper half screen memory 66 and lower half screen memory 67, it is not easy to design the circuit and timing of the display controller, or namely, the LCD controller 68, due to an increase in complexity.
In addition, manufacturing the LCD controller 68 costs much if the concerned electric equipment is in less demand, and makes the resulting electronic equipment expensive. Further, a software program for display must be developed separately for the LCD controller 68.
There is also a problem in the second method in which the frame memory is employed and the address converting circuit 74 is placed before the display controller 73. That is, since the circuit structure of the address converting circuit 74 is complicated and an unillustrated display device controller must be re-designed, the display device controller can not be shared with the other display devices.
Further, since the display data for the upper half and lower half screens are stored separately in the frame memory by converting the addresses, the circuit and interface or the like are undesireably upsized, which makes it almost impossible to place the resulting circuit on an LCD module.